(1.) Field of the Invention
The present invention relates to a semiconductor memory device. In particular, it relates to an improvement of a word line driver in the semiconductor memory device, which driver is arranged between row decoders and a memory cell array constituting an electrically programmable read only memory (EPROM), and supplies a signal having a predetermined level to a selected word line connected to the memory cell array in accordance with signals output from the row decoders when data is written into or read from a predetermined memory cell connected to the selected word line in the memory cell array constituting an EPROM.
(2.) Description of the Related Art
Generally, in an EPROM, the word line driver supplies a write voltage of, for example, d.c. 20 volts, from a d.c. power source for a write mode to a selected word line in accordance with signals output from the row decoders, when data is to be written into a predetermined memory cell connected to the selected word line. Thus, the above write voltage is supplied through the selected word line to a control gate of a cell transistor constituting a memory cell in an EPROM.
During this period (namely, in the write mode), the current flows from a writing circuit through the above cell transistor when predetermined data, for example, "0", is to be written into the predetermined memory cell, and electrons are gradually accumulated in a floating gate of the above cell transistor by supplying the write voltage to the control gate of the above cell transistor.
Therefore, in the cell transistor into which the predetermined data, for example, "0", has been written, the value of the threshold voltage of that cell transistor is increased. As a result, if data, for example, "0", has been written into the memory cell, the corresponding cell transistor does not conduct when the data is to be read from that cell transistor, even if the voltage for a read mode of, for example, d.c. 5 volts, is supplied through the selected word line to the control gate of that cell transistor.
Contrary to this, if the predetermined data, for example "1", is to be written into the predetermined memory cell, the above-mentioned electrons are not accumulated in the above-mentioned floating gate, and therefore, the value of the threshold voltage of the cell transistor is not changed. As a result, when the data, for example, "1", has been written into the memory cell, the corresponding cell transistor conducts by supplying the voltage level for a read mode through the selected word line to the control gate of the cell transistor, to output the read data from that memory cell.
Thus, the kind of data written into each memory cell, namely, "0" and "1", can be read from each memory cell through a sense amplifier by detecting whether or not the corresponding cell transistor is conductive in the read mode.
Further, in an EPROM, after the above-mentioned write process (programming) for each memory cell has been completed, a check is made to determine whether or not the correct data has been written into the corresponding memory cell. This check is generally known as a "Program Verify". Such a check is necessary because, if some of the memory cells are defective, it is possible that incorrect data has been written into those memory cells.
In this connection, when the program is verified, it is necessary to reduce the voltage level of the selected word line from the write mode level (for example, 20 (volts) to the read mode level (for example, 5 volts).
As an explanation of the above, if the voltage level in the write mode is maintained while the program is verified, the cell transistors into which the data "0" or "1" has been written conduct equally when the program is verified, and as a result, it is impossible to check whether the threshold voltage of the cell transistor, into which the predetermined data (for example, "0") has been written, has actually changed as mentioned above.
In the prior art, it is difficult to reduce the voltage level of the selected word line from the write mode level (for example, 20 volts) to the program verify mode level (for example, 5 volts) within a predetermined short time after the write process for each memory cell has been completed.
Therefore, in the prior art, a problem arises in that a predetermined long time after the write process for each memory cell has been completed is required to accurately verify the program written into each memory cell, and as a result, if the program written into each memory cell is verified within the predetermined short time after the write process for each memory cell has been completed, it is impossible to accurately verify the program written into each memory cell, and thus, some memory cells may be judged to be defective cells, even though these memory cells are actually good cells.